VLSI Design and Test 22nd International Symposium VDAT 2018 Madurai India June 28 30 2018 Revised Selected Papers 1st edition by Rajaram, Balamurugan, Gracia Nirmala Rani, Virendra Singh 9811359490 9789811359491

VLSI Design and Test 22nd International Symposium VDAT 2018 Madurai India June 28 30 2018 Revised Selected Papers 1st edition by S. Rajaram, N.B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh – Ebook PDF Instant Download/DeliveryISBN:  9811359490, 9789811359491  

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ISBN-10 :  9811359490 

ISBN-13 :  9789811359491

Author:  S. Rajaram, N.B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh 

This book constitutes the refereed proceedings of the 22st International Symposium on VLSI Design and Test, VDAT 2018, held in Madurai, India, in June 2018. The 39 full papers and 11 short papers presented together with 8 poster papers were carefully reviewed and selected from 231 submissions. The papers are organized in topical sections named: digital design; analog and mixed signal design; hardware security; micro bio-fluidics; VLSI testing; analog circuits and devices; network-on-chip; memory; quantum computing and NoC; sensors and interfaces.

VLSI Design and Test 22nd International Symposium VDAT 2018 Madurai India June 28 30 2018 Revised Selected Papers 1st Table of contents:

1. Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder
2. High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platform
3. A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform
4. Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices
5. Design of High Speed 5:2 and 7:2 Compressor Using Nanomagnetic Logic
6. A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications
7. Analog and Mixed Signal Design
8. A PVT Insensitive Low-Power Differential Ring Oscillator
9. Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
10. A 31 ppm/C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier
11. Supply and Temperature Independent Voltage Reference Circuit in Subthreshold Region
12. CMOS Implementations of Rectified Linear Activation Function
13. Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier
14. Layout Design of X-Band Low Noise Amplifier for Radar Applications
15. Hardware Security
16. A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine
17. Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs
18. Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks
19. SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans
20. A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations
21. Efficient Data Compression Scheme for Secured Application Needs
22. Micro Bio-fluidics
23. Effective Method for Temperature Compensation in Dual Band Metal MEMS Resonator
24. Deadlock Detection in Digital Microfluidics Biochip Droplet Routing
25. Fabrication of Molybdenum MEMs Structures Using Dry and Wet Etching
26. Continuous Flow Microfluidic Channel Design for Blood Plasma Separation
27. Real Time Mixing Index Measurement of Microchannels Using OpenCV
28. Novel RF MEMS Capacitive Switch for Lower Actuation Voltage
29. VLSI Testing
30. A Novel Countermeasure Against Differential Scan Attack in AES Algorithm
31. Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach
32. A Methodology to Design Online Testable Reversible Circuits
33. Robust SRAM Cell Development for Single-Event Multiple Effects
34. Automation of Timing Quality Checks and Optimization
35. Analog Circuits and Devices
36. Temperature Insensitive Low-Power Ring Oscillator Using only n-type Transistors
37. Low-Power Switched Operational Amplifier Using a-InGaZnO TFTs
38. Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study
39. LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits
40. Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO
41. Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology
42. Network-on-Chip
43. Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC
44. A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips
45. Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes
46. 3D LBDR: Logic-Based Distributed Routing for 3D NoC
47. Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization – SoC Approach
48. Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip
49. Memory
50. Efficient and Failure Aware ECC for STT-MRAM Cache Memory
51. A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches
52. Low Leakage Noise Tolerant 10T SRAM Cell
53. A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design
54. Low Leakage Read Write Enhanced 9T SRAM Cell
55. A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) Testing
56. Quantum Computing and NoC
57. A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture
58. Quantum Domain Design of Clifford+T-Based Bidirectional Barrel Shifter
59. Source Hotspot Management in a Mesh Network on Chip
60. An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)
61. Sensors and Interfaces
62. Fabrication and LBM-Modeling of Directional Fluid Transport on Low-Cost Electro-Osmotic Flow Device
63. Fully Digital, Low Energy Capacitive Sensor Interface with an Auto-calibration Unit
64. An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit
65. A Complete Hardware Advent on IEEE 802.15.4 Based Mac Layer and a Comparison with Open-ZB
66. Design of CMOS Based Biosensor for Implantable Medical Devices
67. Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications

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Tags: VLSI Design, International Symposium, Madurai India, Revised Selected, Rajaram, Balamurugan, Gracia Nirmala Rani, Virendra Singh