Low-Power Millimeter Wave Transmitters for High Data Rate Applications 1st edition by Khaled Khalaf, Vojkan Vidojkovic, John R. Long, Piet Wambacq – Ebook PDF Instant Download/DeliveryISBN: 3662469385, 9783662469385
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Product details:
ISBN-10 : 3662469385
ISBN-13 : 9783662469385
Author: Khaled Khalaf, Vojkan Vidojkovic, John R. Long, Piet Wambacq
This book describes the design of a receiver front-end circuit for operation in the 60GHz range in 90nm CMOS. Physical layout of the test circuit and post-layout simulations for the implementation of a test chip including the QVCO and the first stage divider are also presented. The content of this book is particularly of interest to those working on mm-wave frequency generation and signal reception.
Low-Power Millimeter Wave Transmitters for High Data Rate Applications 1st Table of contents:
1 Introduction
1.1 Motivation
1.2 60 GHz Area Background
1.2.1 Standards and Frequency Plan
1.2.2 Beamforming and System Architecture
1.2.3 Enabling Technology
1.2.4 Applications
1.3 Book Objectives
1.4 Organization of the Following Chapters
References
2 Background
2.1 QVCO
2.1.1 VCO Basics
2.1.2 Main Parameters
2.1.3 Phase Noise Origins
2.1.3.1 Resonator Noise
2.1.3.2 Differential Pair Noise
2.1.3.3 Tail Current Noise
2.1.4 Quadrature VCO
2.2 LO Buffer
2.3 Frequency Divider
2.3.1 ILFD
2.3.2 Static Divider
2.4 LNA
2.4.1 NF and IIP3
2.4.2 LNA Topology
2.5 Mixer
2.5.1 Main Parameters
2.5.2 Mixer Topology
References
3 Design and Simulation Results
3.1 fT of the 90 Nm NMOS Transistor
3.2 Passive Elements
3.2.1 Varactors
3.2.2 Transmission Lines
3.2.3 Inductors
3.2.4 Transformers
3.3 QVCO and LO Buffer
3.3.1 Circuit Schematic
3.3.2 Circuit Operation
3.3.2.1 External Gate Bias
3.3.2.2 Modal Determinism
3.3.2.3 Variable Coupling
3.3.2.4 Digital Varactor
3.3.2.5 Current Mirror
3.3.3 Design Guidelines
3.3.3.1 Cross-Coupled Pair
3.3.3.2 Digital Varactor
3.3.3.3 Differential Inductor
3.3.3.4 Quadrature Coupling
3.3.3.5 Current Mirror
3.3.3.6 Current Source
3.3.3.7 Output Voltage Swing
3.3.3.8 External Gate Bias
3.3.3.9 LO Buffer Transistor Size
3.3.3.10 LO Buffer Configuration
3.3.4 Design Values
3.3.5 Simulation Results of P-QVCO
3.3.5.1 Amplitude and Tuning Range
3.3.5.2 Phase Noise
3.3.5.3 Variations with Tail Current
3.3.5.4 Variations with Gate Voltage
3.3.5.5 Variations with Supply Voltage
3.3.5.6 Performance at a Reduced Load Size
3.3.6 Simulation Results of BS-QVCO
3.3.6.1 Performance at a Load Transistor of 40 mu m
3.3.6.2 Performance at a Load Transistor of 24 mu m
3.3.7 Performance Summary
3.4 Divider Chain
3.4.1 Circuit Schematic
3.4.2 ILFD Locking Range
3.4.3 Design Guidelines
3.4.3.1 First Analog Divider Stage
3.4.3.2 Second Analog Divider Stage
3.4.3.3 Static Dividers
3.4.4 Design Values
3.4.5 Simulation Results
3.4.5.1 60 GHz Divider
3.4.5.2 30 GHz Divider
3.4.5.3 First CML Divider
3.4.5.4 Second CML Divider
3.4.5.5 The Complete Divider Chain
3.4.6 Performance Summary
3.5 LNA and Mixer
3.5.1 Circuit Schematic
3.5.2 Design Guidelines
3.5.3 Design Values
3.5.4 Simulation Results
3.5.4.1 Conversion Gain
3.5.4.2 Noise Figure and S11
3.5.4.3 Linearity
3.5.4.4 Results at Reduced Power Consumption
3.5.5 Performance Summary
References
4 Top-Level Design
4.1 Complete Top-Level Circuit
4.1.1 Circuit Schematic
4.1.2 Design Choices
4.1.3 Design Values
4.1.4 Simulation Results
4.2 QVCO and Divider Sub-system
4.2.1 Circuit Schematic
4.2.2 Design Choices
4.2.3 Design Values
4.2.4 Simulation Results
4.2.4.1 Source Follower
4.2.4.2 Divider
4.2.4.3 QVCO and LO Buffer
Reference
5 Layout and Post-layout Simulations
5.1 Physical Layout
5.2 Nominal Simulation Result
5.2.1 Divider
5.2.2 QVCO and LO Buffer
5.3 PVT Simulations
6 Conclusions
6.1 Summary
6.2 Future Work
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Tags: Low Power, Wave Transmitters, Applications, Khaled Khalaf, Vojkan Vidojkovic, John Long, Piet Wambacq