Distributed Real Time Architecture for Mixed Criticality Systems 1st Edition by Hamidreza Ahmadian, Roman Obermaisser, Jon Perez 1351117807 9781351117807

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ISBN-10 ‏ : ‎1351117807 

ISBN-13 ‏ : ‎ 9781351117807

Author: Hamidreza Ahmadian, Roman Obermaisser, Jon Perez 

This book describes a cross-domain architecture and design tools for networked complex systems where application subsystems of different criticality coexist and interact on networked multi-core chips. The architecture leverages multi-core platforms for a hierarchical system perspective of mixed-criticality applications. This system perspective is realized by virtualization to establish security, safety and real-time performance. The impact further includes a reduction of time-to-market, decreased development, deployment and maintenance cost, and the exploitation of the economies of scale through cross-domain components and tools. Describes an end-to-end architecture for hypervisor-level, chip-level, and cluster level. Offers a solution for different types of resources including processors, on-chip communication, off-chip communication, and I/O. Provides a cross-domain approach with examples for wind-power, health-care, and avionics. Introduces hierarchical adaptation strategies for mixed-criticality systems Provides modular verification and certification methods for the seamless integration of mixed-criticality systems. Covers platform technologies, along with a methodology for the development process. Presents an experimental evaluation of technological results in cooperation with industrial partners. The information in this book will be extremely useful to industry leaders who design and manufacture products with distributed embedded systems in mixed-criticality use-cases. It will also benefit suppliers of embedded components or development tools used in this area. As an educational tool, this material can be used to teach students and working professionals in areas including embedded systems, computer networks, system architecture, dependability, real-time systems, and avionics, wind-power and health-care systems.

Distributed Real Time Architecture for Mixed Criticality Systems 1st Table of contents:

1 Introduction
1.1 Context in the Area of Mixed-Criticality Systems
1.2 Scope of the Book
1.3 Motivation and Objectives
1.4 Structure of the Book
2 Architectural Style
2.1 System Model of a Mixed-Criticality System
2.1.1 Physical Platform Structure
2.1.2 Logical Application Architecture
2.1.3 Mapping of Application to Platform
2.2 Waistline Structure of Services
2.2.1 Core Services
2.2.2 Architectural Building Blocks for the Provision of the Platform Services
2.2.3 Communication Services: On-Chip
2.2.4 Communication Services: Off-Chip
2.2.5 Communication Services: Shared Memory
2.2.6 Communication Services: I/O Memory Management Unit and NoC Firewall
2.2.7 Communication Services: Security
2.2.8 Global-Time Service
2.2.9 Integrated Resource Management Services
2.2.10 Execution Services: Software Architecture
2.2.11 Execution Services: DREAMS Virtualization Layer
2.2.12 Execution Services: Security
2.2.13 Optional Service: Voting
2.3 Model-Driven Engineering
2.3.1 Model
2.3.2 Metamodel
2.3.3 Platform-Independent Model
2.3.4 Platform-Specific Model
2.4 Certification Strategy
2.4.1 Safety and Certification
2.4.2 Modular Certification
2.4.3 Mixed-Criticality Patterns
2.4.4 Product Families
2.5 Fault Assumptions
2.5.1 Fault Containment Regions
2.5.2 Failure Modes
2.5.3 Threats
2.6 DHP an Instantiation of the Architectural Style
3 State-of-the-Art and Challenges
3.1 Avionics Domain
3.1.1 State-of-the-Art: Integrated Modular Avionics
3.1.2 Challenges
3.2 Wind-Power Domain
3.2.1 State-of-the-Art: Wind-Turbine Control and Supervision System
3.2.2 State-of-the-Art: Safety Protection System
3.2.3 Challenges
3.3 Health-Care Domain
3.3.1 State-of-the-Art Solutions
3.3.2 Challenges: Platform Security and Functionality
4 Modeling and Development Process
4.1 Introduction
4.1.1 Mixed-Criticality System Modeling Viewpoints
4.1.2 Fundamental Metamodels
4.2 Architecture Design
4.2.1 Logical Modeling Viewpoint
4.2.2 Technical Modeling Viewpoint
4.2.3 Platform Architecture Modeling Framework
4.2.4 Platform Metamodel
4.3 Timing Requirements
4.3.1 Temporal Modeling Viewpoint
4.3.2 Generic Methodology Pattern
4.4 Safety Management
4.4.1 Safety Modeling Viewpoint
4.4.2 Development Process of Safety Solution Design
4.4.3 Verification of Safety Solution Design
4.5 Deployment and Resource Allocation
4.5.1 Deployment Modeling Viewpoint
4.5.2 Resource Allocation Modeling Viewpoint
4.5.3 Basic Deployment and Scheduling Workflow
4.5.4 Adaptivity and Resource Management Workflow
4.6 Service Configuration Generation
4.6.1 Configuration Modeling Viewpoint
4.6.2 Model-transformations and Configuration Synthesis
4.7 Variability and Design Space Exploration
4.7.1 Variability Modeling Viewpoint
4.7.2 Variability Exploration Process
4.7.3 Design-Space Exploration Process
5 Algorithms and Tools
5.1 Variability and Design Space Exploration
5.1.1 Variability Analysis and Testing Techniques
5.1.2 Multi-Objective Design Space Exploration
5.2 Scheduling
5.2.1 Timing Decomposition
5.2.2 Partition Scheduling
5.2.3 On-Chip Network Scheduling
5.2.4 Off-Chip Network Scheduling
5.3 Adaptation Strategies
5.3.1 Recovery Strategies
5.3.2 Comprehensive Offline Schedules
5.3.3 Flexibility
5.4 Timing Analysis
5.4.1 Problem Definition
5.4.2 On-Chip Network
5.4.3 Off-Chip Network
5.4.4 Task Timing Analysis
5.4.5 Composition
5.4.6 Tool: RTaW-Pegase/Timing
5.5 Generation of Configuration Files
5.6 Toolchain
5.6.1 Use Case 1: Basic Scheduling Configuration
5.6.2 Use Case 2: Scheduling Configuration with Resource Management
5.6.3 Use Case 3: Variability and Design-Space Exploration
6 Execution Environment
6.1 Virtualization Technologies
6.1.1 Introduction
6.1.2 Basic Implementation Types: Bare-Metal and Hosted
6.1.3 Provided Virtual Environment Full Virtualization and Para-Virtualization Technology
6.2 Execution Architecture
6.2.1 Hardware Layer
6.2.2 Virtualization Layer
6.2.3 Runtime Layer
6.2.4 Application Layer
6.3 Bare-Metal Hypervisor: XtratuM Case
6.3.1 Overview
6.3.2 System and Partitions Operation
6.3.3 Partitions
6.3.4 Health Monitor
6.3.5 Access to Devices
6.3.6 Services
6.3.7 Configuration
6.3.8 Deployment
6.4 Operating System Hypervisor: Linux-KVM Case
6.4.1 Overview
6.4.2 Scheduling and Coordination for Linux-KVM
6.4.3 ‘Memguard’ to Boost KVM Guests on ARMv8
6.4.4 Secure Monitor Firmware
7 Chip-Level Communication Services
7.1 Bandwidth Regulation Strategies in Linux
7.1.1 Genuine MemGuard Principles and Extensions
7.1.2 Genuine vs. Extended MemGuard (MemGuardXt)
7.1.3 NetGuard Extension (NetGuardXt)
7.2 Hardware MemGuard: Bandwidth Control at Target Devices
7.2.1 Limitations of Hardware MemGuard
7.2.2 Architecture of the Hardware MemGuard
7.2.3 Synthetic Traffic Evaluation
7.2.4 NoC-Based Evaluation
7.3 Hardware Support at Network-on-Chip Level
7.3.1 STNoC Implementation of Address Interleaving
7.3.2 Evaluation Framework: Performance and Power Consumption
7.4 Mixed-Criticality Network-on-Chip
7.4.1 Support for Mixed-Criticality
7.4.2 Support for Heterogeneous Communication Paradigms
7.4.3 Overall Architecture
7.4.4 Network Interface
7.4.5 Core Interface Using Ports
7.4.6 Mixed-Criticality Unit
7.4.7 Back-End
8 Cluster-Level Communication Services
8.1 Off-Chip Network
8.1.1 Time-Triggered Ethernet
8.1.2 EtherCAT
8.2 Security Services
8.2.1 Risk Analysis
8.2.2 Security at Multiple Levels
8.2.3 Security Classification
8.2.4 Cluster-Level Security
8.2.5 Secure Time Synchronization
8.2.6 Application-Level Security
9 Resource Management Services
9.1 Overview of DREAMS Resource Management
9.2 Local Resource Monitor or MON
9.2.1 MON for Core Failure
9.2.2 MON for Deadline Overrun
9.2.3 MON for Quality of Service
9.3 Local Resource Scheduler or LRS
9.3.1 General Approach
9.3.2 Implementation
9.3.3 Requirements on Applications
9.4 Local Resource Manager or LRM
9.4.1 Core Failure Management
9.4.2 Deadline Overrun Management
9.4.3 QoS Management
9.5 Global Resource Manager or GRM
9.5.1 Implementation
9.5.2 Global Reconfiguration Graph
9.6 Resource Management Communication
9.6.1 Secure Resource Management Communication
10 Safety Certification of Mixed-Criticality Systems
10.1 Dreams Safety Certification Strategy
10.2 Certification and Compliant Items
10.2.1 Need and Importance of Certifications
10.2.2 Accreditation
10.2.3 EC Type-Examinations
10.2.4 Certification Requirements According to IEC 61508
10.2.5 Compliant Items According to IEC 61508
10.3 Modular Safety Cases
10.3.1 Modular Safety Case for Cluster-Level Mixed-Criticality Networks
10.4 Mixed-Criticality Patterns
10.4.1 Hypervisors
10.4.2 COTS Multi-Core Device
10.4.3 Mixed-Criticality Network
10.5 Functional Safety Management Process for DREAMS Architecture
10.5.1 IEC 61508 Functional Safety Management
10.5.2 Tools
10.6 Certification of Mixed-Criticality Product Lines
10.6.1 Families of Systems and Product Lines
10.6.2 Piecewise Certification
10.6.3 IEC 61508 Certification
10.7 Method for Certifying Mixed-Criticality Product Lines
10.7.1 Certification Support in DREAMS
10.7.2 Certification Arguments
10.7.3 Database of Argument Models: Mixed-Criticality System
10.7.4 Arguments of Compliance to Safety-Standards
10.7.5 Arguments Based on Verification, Validation and Testing
10.7.6 Summary
11 Evaluation
11.1 Wind-Power Domain
11.1.1 Introduction
11.1.2 Demonstrator Description
11.1.3 Results and Conclusions
11.2 Safety-Critical Domain
11.2.1 Mixed-Criticality and Multi-Cores
11.2.2 Fault Management
11.3 Healthcare Domain
11.3.1 Out-of-Hospital Use-Case: Security-Performance Tradeoffs
11.3.2 In-Hospital Use-Case: Hospital Media Gateway

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Tags: Distributed, Real Time, Architecture, Mixed Criticality, Hamidreza Ahmadian, Roman Obermaisser, Jon Perez