A Primer on Memory Consistency and Cache Coherence 2nd Edition by Vijay Nagarajan, Daniel Sorin, Mark Hill ISBN 1681737108 9781681737102

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ISBN 10:      1681737108
ISBN 13: 978-1681737102
Author:      Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill

A Primer on Memory Consistency and Cache Coherence 2nd Table of contents:

1. Consistency and Coherence Overview

• Consistency (Memory Consistency Model) refers to the rules that define the order in which memory operations (reads/writes) appear to execute across different processors.
• Coherence (Cache Coherence) ensures that multiple copies of the same memory location in different caches stay consistent.
• Both are critical for systems with shared memory to ensure correct operation, especially in parallel computing and heterogeneous systems like GPUs.

2. Coherence Basics

• Coherence Invariants: Conditions that must be satisfied to maintain cache coherence.
• Granularity of Coherence: Determines the smallest unit of memory (e.g., cache line) that coherence applies to.
• Coherence Protocols: Define how caches communicate to maintain coherence (e.g., MSI protocol, which includes Modified, Shared, Invalid states).

3. Memory Consistency Motivation

• The need for a Memory Consistency Model arises to ensure proper sequencing of memory operations across different processors.
• Sequential Consistency (SC): A strict model where the results of execution are as if all memory operations were executed in a single sequence.

4. Sequential Consistency (SC) and Naive Implementations

• SC ensures that the outcome of memory operations is consistent with some sequential order, but can be inefficient in practical implementation.
• Implementations often require optimizations and support for atomic operations and fences to maintain this consistency.

5. Relaxed Memory Models

• Relaxed consistency models, like Total Store Order (TSO) and Release Consistency, allow more flexibility by reordering memory operations to improve performance, but they come with complexities in ensuring correctness.
• XC Model (an example of a relaxed model) demonstrates this by providing examples of fences and atomic instructions to preserve correctness in relaxed models.

6. Coherence Protocols (Snooping and Directory)

• Snooping Protocols: A technique where caches watch (or “snoop on”) the bus to detect memory transactions. Examples include MSI (Modified, Shared, Invalid) and its optimizations with split-transaction buses.
• Directory Protocols: Uses a centralized directory to keep track of which caches hold copies of a particular memory block, avoiding the overhead of broadcasting on a bus.

7. Advanced Coherence Topics

• Discusses complex systems with multi-level caches, virtual caches, and advanced optimization techniques like migratory sharing and false sharing.
• Deals with deadlock, livelock, and starvation, which can occur in systems trying to maintain coherence.

8. Coherence for Heterogeneous Systems (e.g., GPUs)

• Focuses on GPU consistency and coherence in General-Purpose GPU (GPGPU) systems, where traditional models might not apply due to different memory access patterns.
• Topics like temporal coherence and release consistency-directed coherence address the challenges in managing multiple types of memory in heterogeneous environments.

9. Specifying and Validating Models

• Specification of memory models includes operational and axiomatic approaches to define the behavior of memory operations.
• Litmus Tests are used to explore and validate memory models through simple programs that stress-test memory behavior.

 

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