Compiling Algorithms for Heterogeneous Systems Steven Bell

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• ISBN-10 ‏ : ‎ 3031000552
• ISBN-13 ‏ : ‎ 978-3031000553
• Author:  Steven Bell (Author), Jing Pu (Author), James Hegarty (Author), Mark Horowitz (Author)

Most emerging applications in imaging and machine learning must perform immense amounts of computation while holding to strict limits on energy and power. To meet these goals, architects are building increasingly specialized compute engines tailored for these specific tasks. The resulting computer systems are heterogeneous, containing multiple processing cores with wildly different execution models. Unfortunately, the cost of producing this specialized hardware―and the software to control it―is astronomical. Moreover, the task of porting algorithms to these heterogeneous machines typically requires that the algorithm be partitioned across the machine and rewritten for each specific architecture, which is time consuming and prone to error.

Over the last several years, the authors have approached this problem using domain-specific languages (DSLs): high-level programming languages customized for specific domains, such as database manipulation, machine learning, or image processing. By giving up generality, these languages are able to provide high-level abstractions to the developer while producing high-performance output. The purpose of this book is to spur the adoption and the creation of domain-specific languages, especially for the task of creating hardware designs.

In the first chapter, a short historical journey explains the forces driving computer architecture today. Chapter 2 describes the various methods for producing designs for accelerators, outlining the push for more abstraction and the tools that enable designers to work at a higher conceptual level. From there, Chapter 3 provides a brief introduction to image processing algorithms and hardware design patterns for implementing them. Chapters 4 and 5 describe and compare Darkroom and Halide, two domain-specific languages created for image processing that produce high-performance designs for both FPGAs and CPUs from the same source code, enabling rapid design cycles and quick porting of algorithms. The final section describes how the DSL approach also simplifies the problem of interfacing between application code and the accelerator by generating the driver stack in addition to the accelerator configuration.

This book should serve as a useful introduction to domain-specialized computing for computer architecture students and as a primer on domain-specific languages and image processing hardware for those with more experience in the field.

Table of contents:

1. Introduction
2. CMOS Scaling and the Rise of Specialization
3. What Will We Build Now?
4. Performance, Power, and Area
5. Flexibility
6. The Cost of Specialization
7. Good Applications for Acceleration
8. Computations and Compilers
9. Direct Specification
10. Compilers
11. High-level Synthesis
12. Domain-specific Languages
13. Image Processing with Stencil Pipelines
14. Image Signal Processors
15. Example Applications
16. Darkroom: A Stencil Language for Image Processing
17. Language Description
18. A Simple Pipeline in Darkroom
19. Optimal Synthesis of Line-buffered Pipelines
20. Generating Line-buffered Pipelines
21. Shift Operator
22. Finding Optimal Shifts
23. Implementation
24. ASIC and FPGA Synthesis
25. CPU Compilation
26. Evaluation
27. Scheduling for Hardware Synthesis
28. Scheduling for General-purpose Processors
29. Summary
30. Programming CPU/FPGA Systems from Halide
31. The Halide Language
32. Mapping Halide to Hardware
33. Compiler Implementation
34. Architecture Parameter Extraction
35. IR Transformation
36. Loop Perfection Optimization
37. Code Generation
38. Implementation and Evaluation
39. Programmability and Efficiency
40. Quality of Hardware Generation
41. Conclusion
42. Interfacing with Specialized Hardware
43. Common Interfaces
44. The Challenge of Interfaces
45. Solutions to the Interface Problem
46. Compiler Support
47. Library Interface
48. API plus DSL
49. Drivers for Darkroom and Halide on FPGA
50. Memory and Coherency
51. Running the Hardware
52. Generating Systems and Drivers
53. Generating the Whole Stack with Halide
54. Heterogeneous System Performance
55. Conclusions and Future Directions
56. Bibliography

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