Delay Insensitive Circuits Structures Semantics and Strategies 1st Edition Dennis Furey 9781916168107

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• ISBN 13: 9781916168107

• Author: Dennis Furey

 

Delay Insensitive Circuits Structures Semantics and Strategies 1st Table of contents:

1 Why to Study Delay Insensitive Circuits

 1.1 Audience 

1.2 Motivation 

1.2.1 Technological neutrality

1.2.2 Configurable devices

1.2.3 Concurrency theory 

1.3 Random tips on reading this book

2 Why Delay Insensitive Design is Challenging

2.1 How not to do it with logic gates 

2.1.1 Towards a reusable implementation

2.1.2 A concept of signaling protocols 

2.2 How not to do it with DI primitives

2.2.1 Better building blocks 

 2.2.2 Implications of the current solution 

2.2.3 Ways forward from the current solution .

 2.3 How not to compromise 

2.3.1 A two-output primitive

2.3.2 DI versus QDI 

2.3.3 Yet another majority gate

2.3.4 Back to the drawing board 

2.4 Judgment day

2.4.1 What a sequencer does 

2.4.2 How a sequencer enables a majority gate

2.4.3 Implications of this solution 

3 The Lay of the Land

3.1 Overview

3.2 The process model 

3.2.1 Process concepts .

3.2.2 Generality 

3.2.3 Environments 

Block diagrams 

3.3.1 Notation

3.3.2 Methodology 

3.3.3 Flattening

Towards a process semantics

3.4.1 Trace structural composition 

3.4.2 Deficiencies of a naive trace structural composition Petri nets

3.5.1 Notation and conventions of Petri nets 

3.5.2 Expressiveness of Petri nets 

3.5.3 Compositionality of Petri nets 

3.5.4 Limitations of Petri nets 

Procedural description 

3.6.1 Combinator examples

3.6.2 Repetition 

3.6.3 Conditional execution 

3.6.4 Adaptation to an environment 

4 Success

4.1 Reachability graphs 

4.1.1 Example of a reachability graph

4.1.2 Reachability graph algorithms .

 4.2 The transducer model 

4.2.1 Operation

 4.2.2 Limitations 

4.2.3 Utility

4.3 Traces revisited

4.3.1 Progress obligations

4.3.2 Quiescent traces

4.3.3 Refinement 

4.3.4 Trace analysis 

4.4 From transducers to trace recognizers .

4.4.1 A preliminary subgraph 

4.4.2 The complete graph

4.4.3 Edge cases 

4.4.4 Other trace recognizers

4.5 Interim remarks 

II Formal Models

5 Petri Net Plumbing

5.1 Mathematical conventions .

5.1.1 Mapping

5.1.2 Domains and ranges

5.1.3 Cases 

5.1.4 Ordinals 

From Petri nets to processes 

5.2.1 A concrete model

5.2.2 Presets and postsets

5.2.3 Hacking the universe

5.2.4 Open Petri nets 

5.2.5 Process models 

Editing operations 

5.3.1 Rewriting

5.3.2 Sums

5.3.3 Differences 

5.3.4 Completion 

6 Reachability Graph Wrangling

6.1 Math usage 

6.2 Initial reachability graph

6.3 Divergence propagation

6.4 Anonymous edge reduction .

6.5 Redundant path elimination 

6.6 Partition fusion

7 Transducer Tuning

7.1 Finite automata 

7.2.1 Overview

7.3.1 Overview

7.4.1 Non-deterministic relational trace recognizer

7.5.1 Overview

8 Block Building

8.1 On lists

 8.2 Primitive blocks

8.3 Hierarchical blocks

8.4 Netlists

8.5 From hierarchical blocks to netlists

8.6 From hierarchical blocks to primitive blocks

8.7 From blocks and netlists to processes

8.8.1 Schematic capture

9 As Primitive as Can Be

9.3 DI primitives 

 9.4 Generalized DI primitive

10 Decisions

10.1 Ordered trees  .

10.2 Cascading planar decision waits

10.3 Quadrangular decision waits . .

10.4 Multidimensional decision waits 

10.6 Optimized decision waits

11 Thin on the Ground

11.1 Notation . .

11.2 Sparse decision wait transformations 

11.2.3 Permuting the axes 

11.4 Planar sparse decision waits

11.5 Multidimensional sparse decision waits 

11.6 Optimization

 11.7 Verification

12 All About Arbiters

12.1 Notation 

12.2 Arbiter decompositions 

12.3 Transfer functions

12.4 Access patterns

12.5 Metrics 

13 Putting the Word Out

13.1 Pep talk

13.2 Encoders

13.3 Decoders

 Partitionable

13.4 Completion detectors 

14 Working on the Railroad

14.1 Arithmetic units 

14.2 Dual rail to Sperner code conversion 

14.3 Sperner to dual rail conversion 

14.4 Parallelism .

IV Synthesis

15 State Based Synthesis

 15.1 Overview

15.2 Transducer types

5.3 Basic synthesis 

 15.4 Input reduction 

15.5 State reduction 

15.6.1 Decomposition

16 Direct Mapping Synthesis

16.1 Overview 

16.2 Mutual recurrences 16.3 Refined canonical forms 

16.4 Decomposition 

16.5 Interacting state based synthetic communities 

16.6 Interacting direct mapped synthetic communities 

 16.7 State implosion 

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