Digital Systems Design Using VHDL 3rd Edition by Charles Roth, Lizy Kurian John ISBN 9781337515085 1337515086

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Product details:
ISBN 10: 1337515086
ISBN 13: 9781337515085
Author: Charles Roth, Lizy Kurian John
Written for advanced study in digital systems design, Roth/John’s DIGITAL SYSTEMS DESIGN USING VHDL, 3E integrates the use of the industry-standard hardware description language, VHDL, into the digital design process. The book begins with a valuable review of basic logic design concepts before introducing the fundamentals of VHDL. The book concludes with detailed coverage of advanced VHDL topics.

Digital Systems Design Using VHDL 3rd Edition Table of contents:

Ch 1: Review of Logic Fundamentals

1.1 Combinational Logic

1.2 Boolean Algebra and Algebraic Simplification

1.3 Karnaugh Maps

1.4 Designing With NA ND and NOR Gates

1.5 Hazards in Combinational Circuits

1.6 Flip-Flops and Latches

1.7 Mealy Sequential Circuit Design

1.8 Moore Sequential Circuit Design

1.9 Equivalent States and Reduction of State Tables

1.10 Sequential Circuit Timing

1.11 Tristate Logic and Busses

Problems

Ch 2: Introduction to VHDL

2.1 Computer-Aided Design

2.2 Hardware Description Languages

2.3 VHDL Description of Combinational Circuits

2.4 VHDL Modules

2.5 Sequential Statements and VHDL Processes

2.6 Modeling Flip-Flops Using VHDL Processes

2.7 Processes Using Wait Statements

2.8 Two Types of VHDL Delays: Transport and Inertial Delays

2.9 Compilation, Simulation, and Synthesis of VHDL Code

2.10 VHDL Data Types and Operators

2.11 Simple Synthesis Examples

2.12 VHDL Models for Multiplexers

2.13 VHDL Libraries

2.14 Modeling Registers and Counters Using VHDL Processes

2.15 Behavioral and Structural VHDL

2.16 Variables, Signals, and Constants

2.17 Arrays

2.18 Loops in VHDL

2.19 Assert and Report Statements

2.20 Tips for Debugging VHDL Code

Problems

Ch 3: Introduction to Programmable Logic Devices

3.1 Brief Overview of Programmable Logic Devices

3.2 Simple Programmable Logic Devices

3.3 Complex Programmable Logic Devices

3.4 Field Programmable Gate Arrays

3.5 Programmable SoCs (PSOC)

Problems

Ch 4: Design Examples

4.1 BCD to Seven-Segment Display Decoder

4.2 A BCD Adder

4.3 32-Bit Adders

4.4 Traffic Light Controller

4.5 State Graphs for Control Circuits

4.6 Scoreboard and Controller

4.7 Synchronization and Debouncing

4.8 Add-and-Shift Multiplier

4.9 Array Multiplier

4.10 A Signed Integer/Fraction Multiplier

4.11 Keypad Scanner

4.12 Binary Dividers

Problems

Ch 5: SM Charts and Microprogramming

5.1 State Machine Charts

5.2 Derivation of SM Charts

5.3 Realization of SM Charts

5.4 Implementation of the Dice Game

5.5 Microprogramming

5.6 Linked State Machines

Problems

Ch 6: Designing with Field Programmable Gate Arrays

6.1 Implementing Functions in FPGAs

6.2 Implementing Functions Using Shannon’s Decomposition

6.3 Carry Chains in FPGAs

6.4 Cascade Chains in FPGAs

6.5 Examples of Logic Blocks in Commercial FPGAs

6.6 Dedicated Memory in FPGAs

6.7 Dedicated Multipliers in FPGAs

6.8 Cost of Programmability

6.9 FPGAs and One-Hot State Assignment

6.10 FPGA Capacity: Maximum Gates versus Usable Gates

6.11 Design Translation (Synthesis)

6.12 Mapping, Placement, and Routing

Problems

Ch 7: Floating-Point Arithmetic

7.1 Representation of Floating-Point Numbers

7.2 Floating-Point Multiplication

7.3 Floating-Point Addition

7.4 Other Floating-Point Operations

Problems

Ch 8: Additional Topics in VHDL

8.1 VHDL Functions

8.2 VHDL Procedures

8.3 VHDL Predefined Function Called NOW

8.4 Attributes

8.5 Creating Overloaded Operators

8.6 Multivalued Logic and Signal Resolution

8.7 The IEEE 9-Valued Logic System

8.8 SRAM Model Using IEEE 1164

8.9 Model for SRAM Read/Write System

8.10 Generics

8.11 Named Association

8.12 Generate Statements

8.13 Files and TEXTIO

Problems

Ch 9: Design of RISC Microprocessors

9.1 The RISC Philosophy

9.2 The MIPS ISA

9.3 MIPS Instruction Encoding

9.4 Implementation of a MIPS Subset

9.5 VHDL Model of the MIPS Subset

9.6 Design of an ARM Processor

9.7 ARM Instruction Encoding

9.8 Implementation of a Subset of ARM Instructions

9.9 VHDL Model of the ARM Subset

Problems

Ch 10: Verification of Digital Systems

10.1 Importance of Verification

10.2 Verification Terminology

10.3 Functional Verification

10.4 Timing Verification

10.5 Static Timing Analysis for Circuits with No Skew

10.6 Static Timing Analysis for Circuits with Clock Skew

10.7 Glitches in Sequential Circuits

10.8 Clock Gating

10.9 Clock Distribution Circuitry

Problems

Ch 11: Hardware Testing and Design for Testability

11.1 Faults and Fault Models

11.2 Testing Combinational Logic

11.3 Testing Sequential Logic

11.4 Scan Testing

11.5 Boundary Scan

11.6 Memory Testing

11.7 Built-In Self-Test

Problems

Appendix A: VHDL Laguage Summary

Appendix B: IEEE Standard Libraries

Appendix C: TEXTIO Package

Appendix D: Projects

References

Index

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