Languages Design Methods and Tools for Electronic System Design Selected Contributions from FDL 2014 1st Edition by Frank Oppenheimer, Julio Luis Medina Pasaje ISBN 3319244574 9783319244570

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ISBN 10: 3319244574 
ISBN 13: 9783319244570
Author: Frank Oppenheimer, Julio Luis Medina Pasaje

This book brings together a selection of the best papers from the seventeenth edition of the Forum on specification and Design Languages Conference (FDL), which took place on October 14-16, 2014, in Munich, Germany. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

Languages Design Methods and Tools for Electronic System Design Selected Contributions from FDL 2014 1st Table of contents:

Part I Formal Models and Verification and Predictability
1 Automatic Refinement Checking for Formal System Models
1.1 Introduction
1.2 Models and Their Notation
1.3 Refinement of Models
1.4 Theoretical Foundation
1.5 Proposed Solution
1.5.1 Verification Objectives
1.5.2 Basic Encoding
1.5.3 Encoding the Verification Objectives
1.6 Evaluation
1.7 Discussion: Extraction of a Refinement Relation
1.7.1 Existing Approaches
1.7.2 SMT-Based Relation Extraction
1.8 Conclusions
References
2 Towards Simulation Based Evaluation of Safety Goal Violations in Automotive Systems
2.1 Introduction
2.2 Motivation
2.3 Fault Injection by Analogue Saboteurs
2.3.1 Diverse Energy Domain Saboteurs
2.3.2 Design of Generic Saboteurs and Injection into Nominal Model
2.3.2.1 Effect-Based Analogue Saboteur Design
2.3.2.2 Implementation in VHDL-AMS
2.3.2.3 Fault Injection into Nominal Model and Automation
2.4 Case Study: Automotive BMS and EUC
2.4.1 Test-Bench Set-Up
2.4.2 Selected Simulation Results for SPF and Discussion
2.4.3 Selected Simulation Results for Dual-Point Faults and Discussion
2.5 Conclusion and Outlook
References
3 Hybrid Dynamic Data Race Detection in SystemC
3.1 Introduction
3.2 Background
3.2.1 Background on SystemC and Vector Clocks
3.2.2 Background on Dynamic Race Detectors
3.2.2.1 Lockset Based Detector (LBD)
3.2.2.2 Happens-Before Based Detector (HBD)
3.3 Our Hybrid Dynamic Race Detection Algorithm
3.3.1 Algorithm Details
3.3.2 Data Race Detection Examples
3.4 Experimental Results
3.5 Conclusions and Future Works
References
Part II Languages for Requirements
4 Semi-formal Representation of Requirements for Automotive Solutions Using SysML
4.1 Introduction
4.2 Related Work
4.3 Application To Be Modelled
4.3.1 Protected High-Side Switch Description
4.3.1.1 Modelling in SysML
4.3.2 Airbag System
4.3.2.1 Modelling in SysML
4.4 Conclusions
References
5 A New Property Language for the Specification of Hardware-Dependent Embedded System Software
5.1 Introduction
5.2 Low-Level Software Model
5.3 Software Property Language
5.3.1 Interfaces of a Hardware-Dependent Program
5.3.2 Sequences of Variables
5.3.3 Execution Order
5.3.4 Safety and Liveness Properties
5.3.5 Syntax Extensions
5.4 Completeness of Property Sets
5.4.1 Determination Test
5.4.2 Case Split Test
5.4.3 Completeness Criterion
5.5 Case Study
5.6 Conclusion
References
6 Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision
6.1 Introduction
6.2 Typical Methods for Electronic Design Automation
6.2.1 Boolean Satisfiability and SAT Solvers
6.2.2 Applications in EDA
6.3 Formal Representation of Legal Regulations
6.4 Applying EDA Methods to the Formal Representation
6.5 Conclusion
References
Part III Parallel Architectures
7 Synthesizing Code for GPGPUs from Abstract Formal Models
7.1 Introduction
7.2 Background
7.2.1 GPGPUs
7.2.2 ForSyDe
7.3 Synthesis Process
7.3.1 Input Format
7.3.2 Model Optimizations
7.3.3 Process Schedule Generation
7.3.4 Signal Data Type Inference
7.3.5 GPGPU Code Generation
7.3.6 Process Execution and Data Propagation
7.3.7 Limitations
7.4 Experiments
7.4.1 Mandelbrot Tests
7.4.2 Image Processing Tests
7.5 Related Work
7.6 Conclusion
7.7 Future Work
References
8 A Framework for Distributed, Loosely-Synchronized Simulation of Complex SystemC/TLM Models
8.1 Introduction
8.2 SystemC and TLM
8.3 CoMix Fundamentals
8.4 CoMix Framework
8.4.1 CoMix Peer
8.4.2 Connectors
8.4.3 CoMix Multisocket
8.4.4 Framework Characteristics
8.5 Case Study and Results
8.5.1 Setup and Measurements
8.5.2 Achievable Speedup
8.5.3 Synchronization Interval
8.5.4 Temporal Error
8.5.5 Packet Processing Platform
8.6 Related Work
8.7 Conclusion
References
Part IV Modelling and Verification of Power Properties
9 Towards Satisfaction Checking of Power Contracts in Uppaal
9.1 Introduction
9.2 Basic Concept
9.3 Related Work
9.4 Power Contracts
9.5 Leaf-Node Specification with Power Contracts
9.6 Leaf-Node Implementation in UPPAAL
9.6.1 Functionality and Causality
9.6.2 Timing
9.6.3 Power
9.7 Observer Implementation and Verification in UPPAAL
9.8 Proof of Concept
9.8.1 AES Specification
9.8.2 AES Implementation and Characterization
9.8.3 AES Verification
9.9 Conclusion
References
10 SystemC AMS Power Electronic Modelling with Ideal Instantaneous Switches
10.1 Introduction
10.2 Related Work
10.2.1 SystemC Extensions Supporting Electrical Networks
10.2.2 Electrical Networks with Ideal Switches
10.3 Power Electronic Modelling
10.3.1 Abstraction of Power Electronic Circuits
10.3.2 Classes of Switched Networks
10.4 Limitations of Modelling and Simulating Power Electronics in SystemC AMS
10.5 Modelling and Simulating Power Electronics Using Ideal Switches
10.5.1 Computational Advantages of Ideal Switching Modelling
10.5.2 Computational Requirements for Ideal Switching Modelling
10.6 Electrical Piece-Wise-Linear Networks (EPN)
10.6.1 Syntax and Primitives
10.6.2 Network Equations Formulation
10.6.3 Topology Analysis of Switched Electrical Networks
10.6.3.1 Topology Analysis Using a Network Graph
10.6.3.2 Voltage and Current Graphs Analysis
10.6.3.3 Current Graph Topology Analysis Steps
10.6.3.4 Voltage Graph Topology Analysis Steps
10.6.4 Solver Implementation for Switches Networks
10.6.5 Time Step Control
10.6.6 Electrical Circuit Integration in Simulink
10.7 Experimental Results
10.7.1 Buck Converter Simulation
10.7.2 High-Voltage Power Converter Simulation
10.8 Conclusion

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