Systematic Design of Analog CMOS Circuits Using Pre Computed Lookup Tables 1st edition by Paul G. A. Jespers, Boris Murmann 1108135474 9781108135474

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ISBN-10 :  1108135474 

ISBN-13 :  9781108135474

Author:  Paul G. A. Jespers, Boris Murmann 

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Systematic Design of Analog CMOS Circuits Using Pre Computed Lookup Tables 1st table of contents:

1 Introduction
1.1 Motivation
1.2 The Analog Circuit Sizing Problem and the Proposed Approach
1.2.1 Square-Law Perspective
1.2.2 Capturing the Tradeoffs Using Lookup Tables
1.2.3 Generalization
1.2.4 VGS-agnostic design
1.2.5 Design in Weak Inversion
1.3 Content Overview
1.4 Prerequisites
1.5 Notation
1.6 References
2 Basic Transistor Modeling
2.1 The Charge Sheet Model (CSM)
2.1.1 The CSM Drain Current Equation
2.1.2 The Dependence of the Drain Current on the Drain Voltage
2.1.3 The Transconductance Efficiency gm/ID
2.2 The Basic EKV Model
2.2.1 The Basic EKV Equations
2.2.2 The Basic EKV Model for a Grounded-Source MOS Transistor
2.2.3 Strong and Weak Inversion Approximations of the EKV Model
2.2.4 Basic EKV Model Expressions for gm and gm/ID
2.2.5 EKV Parameter Extraction
2.3 Real Transistors
2.3.1 Real Drain Current Characteristics ID(VGS) and gm/ID
2.3.2 The Drain Saturation Voltage VDsat of Real Transistors
2.3.3 Impact of Bias Conditions on EKV Parameters
2.3.4 The Drain Current Characteristic ID(VDS)
2.3.5 The Output Conductance gds
2.3.6 The gds/ID Ratio
2.3.7 The Intrinsic Gain
2.3.8 MOSFET Capacitances and the Transit Frequency fT
2.4 Summary
2.5 References
3 Basic Sizing Using the gm/ID Methodology
3.1 Sizing an Intrinsic Gain Stage (IGS)
3.1.1 Circuit Analysis
3.1.2 Sizing Considerations
3.1.3 Sizing for Given L and gm/ID
3.1.4 Basic Tradeoff Exploration
3.1.5 Sizing in Weak Inversion
3.1.6 Sizing Using the Drain Current Density
3.1.7 Inclusion of Extrinsic Capacitances
3.2 Practical Common-Source Stages
3.2.1 Active Load
3.2.2 Resistive Load
3.3 Differential Amplifier Stages
3.4 Summary
3.5 References
4 Noise, Distortion and Mismatch
4.1 Electronic Noise
4.1.1 Thermal Noise Modeling
4.1.2 Tradeoff between Thermal Noise, GBW and Supply Current
4.1.3 Thermal Noise from Active Loads
4.1.4 Flicker Noise (1/f Noise)
4.2 Nonlinear Distortion
4.2.1 Nonlinearity of the MOS Transconductance
4.2.2 Nonlinearity of the MOS Differential Pair
4.2.3 Inclusion of the Output Conductance
4.3 Random Mismatch
4.3.1 Modeling of Random Mismatch
4.3.2 Effect of Mismatch in a Current Mirror
4.3.3 Effect of Mismatch in a Differential Amplifier
4.4 Summary
4.5 References
5 Practical Circuit Examples I
5.1 Constant Transconductance Bias Circuit
5.2 High-Swing Cascoded Current Mirror
5.2.1 Sizing the Current Mirror Devices
5.2.2 Sizing the Cascode Bias Circuit
5.3 Low-Dropout Voltage Regulator
5.3.1 Low-Frequency Analysis
5.3.2 High-Frequency Analysis
5.4 RF Low-Noise Amplifier
5.4.1 Sizing for Low-Noise Figure
5.4.2 Sizing for Low-Noise Figure and Low Distortion
5.5 Charge Amplifier
5.5.1 Circuit Analysis
5.5.2 Optimization Assuming Constant Transit Frequency
5.5.3 Optimization Assuming Constant Drain Current
5.5.4 Optimization Assuming Constant Noise and Bandwidth
5.6 Designing for Process Corners
5.6.1 Biasing Considerations
5.6.2 Technology Evaluation over Process and Temperature
5.6.3 Possible Design Flows
5.7 Summary
5.8 References
6 Practical Circuit Examples II
6.1 Basic OTA for Switched-Capacitor Circuits
6.1.1 Small-Signal Circuit Analysis
6.1.2 Optimization Assuming Constant Noise and Bandwidth
6.1.3 Optimization in Presence of Slewing
6.2 Folded-Cascode OTA for Switched-Capacitor Circuits
6.2.1 Design Equations
6.2.2 Optimization Procedure
6.2.3 Optimization in Presence of Slewing
6.3 Two-Stage OTA for Switched-Capacitor Circuits
6.3.1 Design Equations
6.3.2 Optimization Procedure
6.3.3 Optimization in Presence of Slewing
6.4 Simplified Design Flows
6.4.1 Folded-Cascode OTA
6.4.2 Two-Stage OTA
6.5 Sizing Switches
6.6 Summary
6.7 References

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Tags: Systematic Design, Analog CMOS, Computed Lookup, Paul Jespers, Boris Murmann